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EEL 3701C - Digital Logic and Computer Systems
Catalog Description: (4 cr) An overview of logic design, algorithms, computer organization and assembly language programming and computer engineering technology. Laboratory.
Prerequisites: Programming
Textbook: Fundamentals of Logic Design, 5th edition. Charles H. Roth, Jr. (2004) ISBN number: 0534378048
Course Objective: perform elementary manipulations of Boolean algebraic equations; simplify logic expressions; design combinational and sequential circuits; use a digital design and simulation package, use a hardware description language (HDL), analyze binary storage device behavior and applications, and to study the fundamentals of microprocessor architecture, including assembly language programming and the design of basic components of a microprocessor.
Professional Component: 2 credits of Engineering Science, 2 credits of Engineering Design
Relationship to Outcomes: (To view how the outcomes of this course fit in with the curriculum, click here)
- EE2 - knowledge of mathematics, basic and engineering sciences necessary to analyze and design complex systems
- b - an ability to design and conduct experiments, as well as to analyze and interpret data
- c - an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability
- e - an ability to identify, formulate, and solve engineering problems
- g - an ability to communicate effectively
- k - an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice
Class Schedule: 3 classes per week of 50 minutes each, 1 3-hour laboratory section
Topics:
- Digital Design; Basic Logic; Mixed Logic
- Intro To Quartus; ICs; Mixed; Positive & Negative Logic; Math Number Systems; Boolean Algebra, K-Maps
- MUX, Demux, Decoder, Encoder, Adder, Other Decoders; Tristate Buffer; ALU
- Sequential Circuits; Flip-Flops; Next State/Excitation Tables; Design with FFs; Counter Design; Debouncing; Intro to VHDL
- RAM, ROM, PLD, CPLD; MAX3000 and MAX7000 CPLDs
- State Machines: Mealy, Moore; ASM Design, Implementations, & ROM Based Designs; Intro to Computer Architecture; Addressing Modes; Data Transfer Instructions
- Instruction Set and Assembly Programming Examples; Basic Computer Operation Cycles and Timing; Memory Maps; G-CPU: Example Processor Design
Course Committee: Dr. Schwartz, Chair, Dr. Lam, Dr. Arroyo, Dr. Fortes
Outcomes assessed in this course. Semester-by-semester histograms for select outcomes for the last two academic years. For previous semesters, click here.
| Academic Year 2005-2006 |
| Fall |
1 |
2 |
3 |
4 |
5 |
Avg |
Outcome b |
0 |
5 |
11 |
18 |
76 |
4.50 |
Outcome c |
7 |
6 |
10 |
23 |
64 |
4.19 |
Outcome k |
0 |
4 |
8 |
18 |
80 |
4.58 |
| Spring |
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Outcome b |
5 |
0 |
4 |
5 |
29 |
4.27 |
Outcome c |
6 |
1 |
3 |
8 |
25 |
3.93 |
Outcome k |
5 |
2 |
5 |
6 |
25 |
3.96 |
| Summer |
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Outcome b |
4 |
5 |
9 |
16 |
30 |
3.98 |
Outcome c |
3 |
2 |
1 |
6 |
52 |
4.59 |
Outcome k |
5 |
0 |
4 |
9 |
46 |
4.42 |
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| Academic Year 2006-2007 |
| Fall |
1 |
2 |
3 |
4 |
5 |
Avg |
Outcome b |
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Outcome c |
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Outcome k |
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| Spring |
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Outcome b |
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Outcome c |
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Outcome k |
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| Summer |
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Outcome b |
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Outcome c |
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Outcome k |
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Course Committee Reports for:
| Fall Term |
Spring Term |
Summer Term |
| 2005 |
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2006 |
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