EEL 4712C - Digital Design

 

Catalog Description: (4 cr) Advanced modular logic design, design languages, "finite" state machines and binary logic. Laboratory.

Prerequisites: Digital Logic and Computer Systems

Textbook: Fundamentals of Digital Logic with VHDL Design, 2nd Ed. S.D. Brown and Z.G. Vranesic, ISBN number: 0-07-246085-7

Course Objective: The objective of this course is to study the fundamentals, methodologies, and techniques for the structured design of digital systems, using the state of the art technologies and design environments and tools.

Professional Component: 4 credits of Engineering Design

Relationship to Outcomes:  (To view how the outcomes of this course fit in with the curriculum, click here) 

• EE2 - knowledge of mathematics, basic and engineering sciences necessary to analyze and design complex systems
• a - an ability to apply knowledge of mathematics, science, and engineering
• c - an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability
• e - an ability to identify, formulate, and solve engineering problems
• k - an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice

Class Schedule:  3 classes per week of 50 minutes each, 1 3 hour laboratory section

Topics:

I. Digital design technologies

• Review, VHDL Implementation
• Carry-look-ahead adders, ALUs.
• Programmable logic devices: PAL's, PLA's, PROM's, CPLD's, and FPGA's
• Memories - RAM, DRAM, and ROM

II. Digital design methodology and techniques for finite state machines (FSM)

• Top-down, modular design
• Controller/controlled-component architecture
• ASM fundamentals and design methods 
• Implementation methods - traditional, MUX, ROM, "one-hot", CPLD's, FPGA's 
• Testing and design for testing

III. Design environments and tools (lab-intensive)

• Design life cycle using model digital development environment
• Design specification: graphical, VHDL
• Logic synthesis
• Simulation: functional and timing
• Timing analysis
• Device program
• Testing

Ciourse Committee:  Dr. Lam, Chair, Dr. Figueiredo, Dr. Schwartz

Course Committee Reports for:

Fall Term		Spring Term		Summer Term
2005